GDC21D601 Datasheet, PDF (113/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
NAME
EPG[7:0]
PGOE[7:0]
PH[7:0]
EPH[7:0]
PHOE[7:0]
PI[7:0]
EPI[7:0]
PIOE[7:0]
PJ[7:0]
EPJ[7:0]
PJOE[7:0]
TYPE
I
O
O
I
O
O
I
O
O
I
O
SOURCE/
DESTINATION
PADS
PADS
PADS
PADS
PADS
PADS
PADS
PADS
PADS
PADS
PADS
DESCRIPTION
Port G input driver. It reflects the external state of the port. This
information is obtained when the PGDR register is read.
Port G output enable (active LOW). Values written on PGDDR
register are put onto these lines.
Port H output driver. Values written on PHDR register are put onto
these lines and driven out to the port H pins if the corresponding data
direction bits are set to HIGH (PHDDR register).
Port H input driver. It reflects the external state of the port. This
information is obtained when the PHDR register is read.
Port H output enable (active LOW). Values written on PHDDR
register are put onto these lines.
Port I output driver. Values written on PIDR register are put onto these
lines and driven out to the port I pins if the corresponding data
direction bits are set to HIGH (PIDDR register).
Port I input driver. It reflects the external state of the port. This
information is obtained when the PIDR register is read.
Port I output enable (active LOW). Values written on PIDDR register
are put onto these lines.
Port J output driver. Values written on PJDR register are put onto these
lines and driven out to the port J pins if the corresponding data
direction bits are set to HIGH (PJDDR register).
Port J input driver. It reflects the external state of the port. This
information is obtained when the PJDR register is read.
Port J output enable (active LOW). Values written on PJDDR register
are put onto these lines.
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