GDC21D601 Datasheet, PDF (118/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
2. Signal Description
The SSPI module is connected to the APB bus. Table 1. Signal descriptions describe the APB signals used and
produced. Table 2. Signal descriptions show the non-AMBA signals from the block.
NAME
BnRES
PA[5:2]
PD[7:0]
PSTB
PWRIT
E
PSEL
TYPE
I
I
I/O
I
I
I
Table 1. Signal Descriptions
SOURCE/
DESTINATION
PMU
APB Bridge
APB Peripherals,
B_D
APB Bridge
APB Bridge
APB Bridge
DESCRIPTION
ASB reset signal (active LOW).
This is the part of the peripheral address bus, and is used by the
peripheral for decoding its own register accesses.
The addresses become valid before PSTB goes to HIGH and remain
valid after PSTB goes to LOW.
This is the part of the bi-directional peripheral data bus. This block
drives the data bus during read cycles (when PWRITE is LOW).
This strobe signal is used to time all accesses on the peripheral bus.
The falling edge of PSTB is coincident with the falling edge of
B_CLK (ASB system clock).
When this signal is HIGH, it indicates a write to a peripheral, when
this signal is LOW, it indicates a read from a peripheral.
This signal has the same timing as the peripheral address bus. It
becomes valid before PSTB goes to HIGH and remains valid after
PSTB goes to LOW.
When this signal is HIGH, this signal indicates that the APB bridge
has selected the SSPI module. This selection is a decode result of
the system address bus. For more details, see AMBA Peripheral Bus
Controller.
NAME
CLK
SSIIN
SSIOUT
SSICS
SCLK
SSIIRQ
TYPE
I
I
O
I/O
I/O
O
Table 2. Specific Block Signal Descriptions
SOURCE/
DESTINATION
PMU
SSIIN pad
SSIOUT pad
SSICS pad
SCLK pad
Interrupt
Controller
DESCRIPTION
SSPI clock input at a frequency of 3.68MHz., scaled /4, /8, /32, /64
Serial data input.
Serial data output.
Chip select signal.
Serial data clock to the external SSI.
Active HIGH Interrupt Request.
119