GDC21D601 Datasheet, PDF (65/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

7. Signal Timing Diagram
The PMU signal timing is as shown below.
7.1 Power on Reset
S_CLK
RESETn_IN
B_RESETn
P_RESETn0/1
RESETn_OUT
Figure 5. Power on Reset Timing Diagram
7.2 Watch Dog Timer Overflow
B_CLK
WD_OF_IN
WD_OF_OUT
B_RESETn
P_RESETn0/1
256 B_CLK
512 B_CLK
GDC21D601
Figure 6. Watch Dog Timer Overflow Timing Diagram
7.3 Manual Reset
There are two manual reset cases. The first reset operation is switched by MAN_RST signal from WDT. Another
case is called S/W reset.
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