GDC21D601 Datasheet, PDF (157/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
2. Signal Description
NAME
BCLK
BnRES
BA[31:0]
BD[31:0]
AREQ
AGNT
BERROR
BLAST
BLOCK
BPROT[1:0]
BSIZE[1:0]
BTRAN[1:0]
BWAIT
BWRITE
DSEL
nDMAReq[1:0]
nDMAck[1:0]
DMAtrans
TRendINT
Table 1. DMA Controller Signal Descriptions
TYPE
I
I
I/O
I/O
O
I
I/O
I/O
O
O
O
O
I/O
I/O
I
I
I
O
O
DESCRIPTION
AMBA System bus clock. This clock times all bus transfers.
The clock has two distinct phases - phase 1 where BCLK is LOW, and phase 2
where BCLK is HIGH.
This signal indicates the reset status of the bus.
ASB address. Output for DMAC operation. Input for Register access.
This is the part of Bi-directional system data bus.
Request signal for ASB Bus mastership.
Bus Grant signal from ASB arbiter.
ASB error signal.
ASB break burst signal from DRAM Controller.
ASB locked transfer signal
ASB master protection information.
ASB transaction size signal.
ASB transaction type signal.
ASB wait transfer signal. Input for DMA cycle stretch.
Out for Register access.
ASB transfer direction signal
Register select signal
DMA transfer request signal from the external I/O device. These are connected to
nDMAReq[1:0] pins
DMA transfer acknowledge signal to the external I/O device. These are connected
to nDMAAck[1:0] pins.
Indicate the DRAM access during DMA transfer. This signal connected to DRAM
Controller.
DMA transfer end interrupt signal to CPU
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