GDC21D601 Datasheet, PDF (89/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
(8) IRQ Mask Register
Readable and Writable. The IRQ request mask register is used to mask the request to generate an interrupt to a
processor. If certain bits within the interrupt controller are not implemented, the corresponding bits in the IRQ
request mask register must be masked. A bit value 0 indicates that the interrupt is unmasked and will allow an
interrupt request to reach the processor. A bit value 1 indicates that the interrupt is masked. On reset, all IRQ
requests are unmasked.
‘1’ : Request Mask
‘0’ : Request Unmask
Initial value : 0x0000000
25
0
00000000000000000000000000
(9) Status Clear Register
Write-only. The status clear register is used to clear bits in the status register configured to the edge trigger mode.
If the channels are configured to the level trigger mode, the corresponding bits in the FIQ status register and the
IRQ status register have no effect. This register is cleared when the signal, P_STB, is LOW after this register is
written to ‘1’. When writing to this register, each data bit that is HIGH causes the corresponding bit in the status
register to be cleared. Data bits that are LOW have no effect on the corresponding bit in the status register. Note
that the status clear register has an effect on the status register in the edge trigger mode.
‘1’ : Clear the status register
‘0’ : Not clear
Initial value : 0x0000000
25
0
00000000000000000000000000
90