GDC21D601 Datasheet, PDF (136/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
Table 9. Interrupt Control Functions
FIFO
MODE
ONLY
Bit 3
0
0
0
1
0
0
INTERRUPT
IDENTIFICATION
REGISTER
Bit 2 Bit 1 Bit 0
0
0
1
1
1
0
1
0
0
1
0
0
0
1
0
0
0
0
INTERRUPT SET AND RESET FUNCTIONS
Priority Level Interrupt Type Interrupt Source
Interrupt
Reset Control
-
None
None
-
Highest
Receiver
Overrun Error, Parity Error, Framing Reading the Line
Line Status Error or Break Interrupt
Status Register
Second
Receiver
Receiver Data Available or Trigger Reading the Receiver
Data Available Level Reached
Buffer Register or the
FIFO drops below the
trigger level
Second
Character
No Characters have been removed Reading the Receiver
Time-out
from or input to the RCVR FIFO Buffer Register
Indication
during the last 4 Char. times and
there is at least 1 Char. in it during
this time
Third
Transmitter Transmitter Holding Register Empty Reading the IIR
Holding
Register (if it is the
Register
source of interrupt) or
Empty
writing it into the
Transmitter Holding
Register
Fourth
MODEM
Clear to Send, Data Set Ready, Ring Reading
the
Status
Indicator, or Data Carrier Detect MODEM Status
Register
Interrupt Enable Register
This register enables the five types of UART interrupts. Each interrupt can individually activate the interrupt
(INT_UART) output signal. It is possible to totally disable the interrupt Enable Register (IER). Similarly, setting
bits of the IER register to a logic 1 enable the selected interrupt(s). Disabling an interrupt prevents it from being
indicated as active in the IIR and from activating the INT_UART output signal. All other system functions operate
in their normal manners, including the setting of the Line Status and MODEM Status Registers. Table 5. Summary
of Registers shows the contents of the IER. Details on each bit are :
Bit 0 : This bit enables the Received Data Available Interrupt (and time-out interrupts in the FIFO mode) when
it is set to logic 1.
Bit 1 : This bit enables the Transmitter Holding Register Empty Interrupt when set to logic 1.
Bit 2 : This bit enables the Receiver Line Status Interrupt when it is set to logic 1.
Bit 3 : This bit enables the MODEM Status Interrupt when it is set to logic 1.
Bit 4 through 7 :These four bits are always logic 0.
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