GDC21D601 Datasheet, PDF (19/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
Section 2. System Architecture
1. Internal Bus Architecture
The GDC21D601 take the advantage of the AMBA(Advanced Micro-controller Bus Architecture) as the internal
Bus Architecture. The AMBA specification defines an on-chip communication standard for designing high-
performance embedded micocontrollers. Two distinct buses are defined within the AMBA:
- the Advanced System Bus (ASB)
- the Advanced Peripheral Bus (APB)
The AMBA ASB is for high-performance system modules. The modules connected to ASB are DRAM Controller,
Static Memory Controller, DMA Controller, On-Chip SRAM, ARM720T CPU Core, Arbiter, Decoder, APB
Bridge, and TIC.
The AMBA APB is for low-power peripherals. AMBA APB is optimized for minimal power consumption and
reduced interface complexity to support peripheral functions. The modules connected to APB are PIO, Interrupt
Controller, PMU, WDT, RTC, Timer, UART, SSPI, and I²C.
See also AMBA Specification Rev. D (ARM IHI 0001D), and AMBA Specification Rev. 2.0 (ARM IHI 0011A)
for detail.
2. Arbiter
The AMBA bus specification is a multi-master bus standard. As a result, a bus arbiter is needed to ensure that only
one bus master has an access to the bus at any particular point of time. Each bus master can request the bus; the
Arbiter decides which has the highest priority and issues a grant signal accordingly. The GDC21D601 can have the
four bus master: ARM720T CPU Core, DMA Controller, TIC, and External Bus Master.
Every system must have a default bus master which grants the use of bus during reset, when no other bus master
requires the bus. During Power On Reset, the arbiter will grant the use of bus to the default bus master and hold all
other grant signals inactive. The ARM720T Core, the default bus master will grant for the use of bus under the
following conditions: Reset, standby, power-down, and no other master requesting the bus
The arbiter processes the requests of the ownership of the ASB and grants one ASB master according to the
arbitration scheme. The arbitration scheme of this implementation is a simple priority encoded scheme where the
highest priority master requesting the ASB is granted. The priority order is as follows:
Case 1) Aripri = ‘0’
1. TIC
2. DMA
3. External BUS Master
4. ARM (default bus master)
Case 2) Aripri = ‘1’
1. TIC
2. External BUS Master
3. DMA
4. ARM (default bus master)
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