GDC21D601 Datasheet, PDF (152/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

6.3 I²C Address Register (addr_r).
GDC21D601
The addr_r is an 8-bit write-only register that is used to be accessed by other master.
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addr_r
BIT NAME
FUNCTION
7:0 addr_r
Indicates the slave address of the I²C controller.
This address is used in comparing the incoming addresses in slave mode
6.4 I²C Baud-Rate Register (baud_r).
I²C block uses the clock generated by dividing system clock which is set in baud_r. Additionally this clock is used
to generate the SCL clock which is eight-divided by internal clock. The default value is 4. Assuming system clock
is 29Mhz, SCL clock is 300kHz and maximum SCL frequency is 1.8Mhz
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baud_r
BIT NAME
FUNCTION
7:0 baud_r
indicates the clock dividing value whose clock signal is used in internal operation internal
clock frequency is (baud_r + 2) *2 and when it is set as 255, the internal clock is half-
divided .
6.5 I²C Data Register (data_r).
Data register is the 8bit read/write register which is used to send or receive data. Internally this register consists of
two registers, transmit register and receive register respectively. Written data is transferred to transmit register, and
read data from receive register. In every phase, SDA line is driven by transmit register and SDA line is read by
receive register.
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data_r
BIT NAME
FUNCTION
7:0 data_r
Written data is serially transmitted through the SDA line, and SDA line data is written In
receive register
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