GDC21D601 Datasheet, PDF (47/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
Section 7. MCU Controller
1. General Description
Designing the Microcontroller unit (MCU), some control signals needed by any functional block, but not drive any
other block, must be generated. So these control signals are generated in MCU Controller. The MCU Controller
(MCUC) is composed of registers which are for selecting the function of multi-function pins, for defining the
memory map structure, arbiter priority, MCU device code, and DRAM Power Down Req/Ack signals.
2. Signal Description
NAME
BCLK
BnRES
BA[31:0]
BD[31:0]
BWAIT
BLAST
BERROR
BWRITE
DSEL
PwrDwnAck
PwrDwnReq
Ari_pri
Isram
Drambank0
PINMUX_sigs
TYPE
I
I
I
I/O
O
O
O
I
I
I
O
O
O
O
O
Table 1. Signal Descriptions
DESCRIPTION
System bus clock.
the reset status of the ASB
System address bus
Bi-directional system data bus.
Low during phase one of BCLK
Low during phase one of BCLK
Low during phase one of BCLK
When this signal is HIGH, it indicates a write transfer and when LOW a read.
When this signal is HIGH, it indicates that MCU Controller is selected.
This signal indicates that DRAM is entered into self-refresh mode
The request of entering the self-refresh node of DRAM
Determine Arbiter Priority. See Section.2 System Architecture for detail
Allocate On-Chip SRAM address area at 0x00000000
Allocate DRAM address area at 0x00000000
These signals are for Multi-function pin
48