GDC21D601 Datasheet, PDF (124/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
Section 15. UART
1. General Description
This module is an Universal Asynchronous Receiver/Transmitter(UART) with FIFOs, and is functionally identical
to the 16450 on power-up (CHARACTER mode). The GM16550 can be put into an alternate mode (FIFO mode)
to relieve the CPU of excessive software overhead.
In this mode internal FIFOs are activated allowing 16 bytes plus 3 bit of error data per byte in the RCVR FIFO, to
be stored in both receive and transmit modes. All the logic is on the chip to minimize the system overhead and
maximize system efficiency.
The UART performs serial-to-parallel conversion on data characters received from a peripheral device or a
MODEM and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the
complete status of the UART at any time during the functional operation. Status information reported includes
the type and condition of the transfer operations performed by the UART, as well as any error conditions(parity,
overrun, framing, or break interrupt).
The UART includes a programmable baud rate generator that is capable of dividing the timing reference clock
input by divisors of 1 to 65535 and producing a 16x clock for driving the internal transmitter logic. Provisions are
also included to use this 16x clock to drive the receiver logic.
The UART has complete MODEM-control capability and a processor-interrupt system. Interrupts can be
programmed to the user’s requirements, minimizing the computing required to handle the communications link.
2. Features
• Capable of running all existing 16450 software.
• After reset, all registers are identical to the 16450 register set.
• The FIFO mode transmitter and receiver are each buffered with 16 byte FIFO’s to reduce the number of
interrupts presented to the CPU.
• Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data.
• Hold and shift registers in the 16450 mode eliminate the need for precise synchronization between the CPU and
serial data.
• Independently controlled transmit, receive, line status and data set interrupts.
• Programmable baud generator divides any input clock by 1 to 65535 and generates 16x clock
• Independent receiver clock input.
• MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD).
• Fully programmable serial-interface characteristics:
5-, 6-, 7- or 8-bit characters
Even, odd, or no-parity bit generation and detection
1-, 1.5- or 2-stop bit generation and detection
Baud generation (DC to 256k baud)
• False start bit detection.
• Complete status reporting capabilities.
• Line break generation and detection.
• Internal diagnostic capabilities.
• Loopback controls for communications link fault isolation
• Full prioritized interrupt system controls.
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