GDC21D601 Datasheet, PDF (122/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
5. Register Memory Map
The base address of the SSPI interface is 0xFFFF F800 and the offset of any particular register from the base
address is as followed.
ADDRESS
SSI Base
SSI Base + 0x04
SSI Base + 0x08
SSI Base + 0x0C
SSI Base + 0x10
SSI Base + 0x20
SSI Base + 0x24
SSI Base + 0x28
SSI Base + 0x2C
SSI Base + 0x30
READ LOCATION
SSCR0
SSCR1
SSDR
SSSR
SSCR0
SSCR1
SSDR
SSSR
WRITE LOCATION
SSCR0
SSCR1
SSDR
SSTR
SSCR0
SSCR1
SSDR
SSTR
SSCR0 : Control Register0
SSCR1 : Control Register1
SSDR : Data Register
SSSR : Status Register
SSTR : Term Register
SSI Register Memory Map
The output frequency is selected by programming the lower two bits of the SSCR1 register, SSCR1[1:0]. The
following table shows the possible settings:
SSCR1[1..0]
DIV
00
4
01
8
10
32
11
64
FREQUENCY (WHEN PCLK=3.6864MHZ)
921.6 KHz
460.8 KHz
115.2 KHz
57.6 KHz
SSCR1[1:0] Encoding
123