MC68HC08AZ0 Datasheet, PDF (96/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
System Integration Module (SIM)
Illegal opcode
reset
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
If the STOP enable bit, STOP, in the mask option register is logic ‘0’, the
SIM treats the STOP instruction as an illegal opcode and causes an
illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
Illegal address
reset
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register SRSR) and
resetting the MCU. A data fetch from an unmapped address does not
generate a reset. The SIM actively pulls down the RST pin for all internal
reset sources.
NOTE:
Extra care should be exercised if off-chip code is eventually ported
into another HC08 with a smaller on-chip ROM since some legal
addresses could become illegal addresses on a smaller ROM. It is
the user’s responsibility to check their code for illegal addresses.
Low-voltage
inhibit (LVI) reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the V_DD voltage falls to the LVI_TRIPF voltage. The LVI bit in the SIM reset
status register (SRSR) is set, and the external reset pin (RST) is held low
while the SIM counter counts out 4096 CGMXCLK cycles. 64 CGMXCLK
cycles later, the CPU is released from reset to allow the reset vector
sequence to occur. The SIM actively pulls down the RST pin for all
internal reset sources.
MC68HC08AZ0
94
System Integration Module (SIM)
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