MC68HC08AZ0 Datasheet, PDF (298/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Timer Interface Module B (TIMB)
When ELSxB:A = 00, this read/write bit selects the initial output level
of the TCHx pin. See Table 1. Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE:
Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIMB status and control register
(TSC).
ELSxB and ELSxA — Edge/level select bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to port F, and pin PTFx/TBCHx is available as a general-purpose I/O
pin. Table 1 shows how ELSxB and ELSxA work. Reset clears the
ELSxB and ELSxA bits.
Table 1. Mode, edge, and level selection
MSxB:MSxA ELSxB:ELSxA
X0
00
X1
00
00
01
00
10
00
11
01
01
01
10
01
11
1X
01
1X
10
1X
11
Mode
Output Preset
Input Capture
Output
Compare or
PWM
Buffered
Output
Compare or
Buffered PWM
Configuration
Pin under Port Control; Initial Output Level High
Pin under Port Control; Initial Output Level Low
Capture on Rising Edge Only
Capture on Falling Edge Only
Capture on Rising or Falling Edge
Toggle Output on Compare
Clear Output on Compare
Set Output on Compare
Toggle Output on Compare
Clear Output on Compare
Set Output on Compare
MC68HC08AZ0
296
Timer Interface Module B (TIMB)
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20-timb
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