MC68HC08AZ0 Datasheet, PDF (350/444 Pages) Motorola, Inc – Advance Information

I/O Ports
Freescale Semiconductor, Inc.
DDRG[2:0] — Data direction register G bits
These read/write bits control port G data direction. Reset clears
DDRG[2:0], configuring all port G pins as inputs.
1 = Corresponding port G pin configured as output
0 = Corresponding port G pin configured as input
NOTE: Avoid glitches on port G pins by writing to the port G data register before
changing data direction register G bits from 0 to 1.
Figure 21 shows the port G I/O logic.
READ DDRG ($000E)
WRITE DDRG ($000E)
RESET
WRITE PTG ($000A)
READ PTG ($000A)
DDRGx
PTGx
PTGx
Figure 21. Port G I/O circuit
When bit DDRGx is a logic one, reading address $000A reads the PTGx
data latch. When bit DDRGx is a logic zero, reading address $000A
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data.
MC68HC08AZ0
348
I/O Ports
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