MC68HC08AZ0 Datasheet, PDF (303/444 Pages) Motorola, Inc – Advance Information

PIT counter
prescaler
Freescale Semiconductor, Inc.
Programmable Interrupt Timer (PIT)
Low-power modes
The clock source can be one of the seven prescaler outputs. The pres-
caler generates seven clock rates from the internal bus clock. The pres-
caler select bits, PPS[2:0] in the status and control register select the
PIT clock source.
The value in the PIT counter modulo registers and the selected pres-
caler output determines the frequency of the Periodic Interrupt. The PIT
overflow flag (POF) is set when the PIT counter value rolls over to
$0000 after matching the value in the PIT counter modulo registers. The
PIT interrupt enable bit, PIE, enables PIT overflow CPU interrupt
requests. POF and PIE are in the PIT status and control register.
Low-power modes
The WAIT and STOP instructions put the MCU in low-power-consump-
tion standby modes.
WAIT mode
The PIT remains active after the execution of a WAIT instruction. In wait
mode the PIT registers are not accessible by the CPU. Any enabled
CPU interrupt request from the PIT can bring the MCU out of wait
mode.
If PIT functions are not required during wait mode, reduce power con-
sumption by stopping the PIT before executing the WAIT instruction.
STOP mode
The PIT is inactive after the execution of a STOP instruction. The STOP
instruction does not affect register conditions or the state of the PIT
counter. PIT operation resumes when the MCU exits stop mode after an
external interrupt.
3-pit
MOTOROLA
Programmable Interrupt Timer (PIT)
For More Information On This Product,
Go to: www.freescale.com
MC68HC08AZ0
301