MC68HC08AZ0 Datasheet, PDF (323/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Keyboard Module (KB)
Functional description
Table 1. KB I/O register summary
Register Name
Bit 7 6
5
4
3
2
1 Bit 0 Addr.
Keyboard Status/Control ^{R: 0}
Register (KBSCR) _W:
0
0
0
KEYF
0
ACKK
IMASK MODE
K
K
$001B
Reset
0
0
0
0
0
0
0
0
Keyboard Interrupt Control ^{R: 0}
Register (KBICR) _W:
0
0
KB4IE KB3IE KB2IE KB1IE KB0IE $0021
Reset
0
0
0
0
0
0
0
0
= Unimplemented
The MODEK bit in the keyboard status and control register controls the
triggering sensitivity of the keyboard interrupt latch. If the MODEK bit is
set, the keyboard interrupt pins are both falling-edge- and
low-level-sensitive, and both of the following actions must occur to clear
the keyboard interrupt latch:
• Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic one to
the ACKK bit in the keyboard status and control register (KBSCR).
The ACKK bit is useful in applications that poll the keyboard
interrupt pins and require software to clear the keyboard interrupt
latch. Writing to the ACKK bit can also prevent spurious interrupts
due to noise. Setting ACKK does not affect subsequent transitions
on the keyboard interrupt pins. A falling edge that occurs after
writing to the ACKK bit latches another interrupt request. If the
keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the
program counter with the vector address at locations $FFD2 and
$FFD3.
• Return of all enabled keyboard interrupt pins to logic one — As
long as any enabled keyboard interrupt pin is at logic zero, the
keyboard interrupt latch remains set.
The vector fetch or software clear and the return of all enabled keyboard
interrupt pins to logic one may occur in any order. The interrupt request
remains pending as long as any enabled keyboard interrupt pin is at
logic zero.
3-kbd
MOTOROLA
Keyboard Module (KB)
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MC68HC08AZ0
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