MC68HC08AZ0 Datasheet, PDF (31/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Memory Map
I/O section
Addr.
$002D
$002E
$002F
$0030
$0031
$0032
$0033
$0034
$0035
$0036
$0037
$0038
$0039
$003A
$003B
Name
Timer A Channel 2 R:
Register High (TACH2H) W:
Timer A Channel 2 R:
Register Low (TACH2L) W:
Timer Channel 3 Status R:
and Control Register
(TASC3)
W:
Timer Channel 3 Register R:
High (TACH3H) W:
Timer Channel 3 Register R:
Low (TACH3L) W:
Unimplemented
R:
W:
Unimplemented
R:
W:
R:
Unimplemented
W:
Unimplemented
R:
W:
Unimplemented
R:
W:
R:
Unimplemented
W:
R:
ADSCR
W:
R:
ADR
W:
ADC Input Clock Select R:
(ADCLKR) W:
EBI COntrol Register
R:
(EBIC)
W:
Bit 7
Bit 15
Bit 7
CH3F
0
Bit 15
Bit 7
COCO
R
AD7
ADIV2
0
6
14
6
CH3IE
14
6
AIEN
AD6
ADIV1
IRV
5
13
5
MS3B
13
5
ADCO
AD5
ADIV0
NODE
4
3
2
1
Bit 0
12
11
10
9
Bit 8
4
3
2
1
Bit 0
MS3A ELS3B ELS3A TOV3 CH3MAX
12
11
10
9
Bit 8
4
3
2
1
Bit 0
CH4
AD4
CH3
AD3
ADICLK
0
CH2
AD2
0
CH1
AD1
0
CH0
AD0
0
CS0WS MODE WSCLK0 CSC1 CSC0
$003C
EBI Chip Select Register
(EBICS)
R:
W: CS1WS1 CS1WS0 CS1POL
CS1EN CS0WS1 CS0WS0 CS0POL CS0EN
R:
$003D
Unimplemented
W:
$003E
Unimplemented
R:
W:
$003F
Mask Option Register B R:
(MORB) W:
R
R
EESEC
R
R
R
R
R
$0040
TimerB Status and Control R:
Register (TBSC) W:
TOF
0
TOIE
TSTOP
0
TRST
0
PS2
PS1
PS0
$0041
TimerB Counter Register R: Bit 15
High (TBCNTH) W:
14
13
12
11
10
9
8
= Unimplemented
R = Reserved
Figure 5. Control, status, and data registers (Sheet 3 of 5)
7-mem
MOTOROLA
Memory Map
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MC68HC08AZ0
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