MC68HC08AZ0 Datasheet, PDF (126/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
ACQ — Acquisition mode bit
When the AUTO bit is set, ACQ is a read-only bit that indicates
whether the PLL is in acquisition mode or tracking mode. When the
AUTO bit is clear, ACQ is a read/write bit that controls whether the
PLL is in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written
value from manual operation is stored in a temporary location and is
recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Tracking mode
0 = Acquisition mode
XLD — Crystal loss detect bit
When the VCO output, CGMVCLK, is driving CGMOUT, this
read/write bit indicates whether the crystal reference frequency
is active or not. To check the status of the crystal reference, the
following procedure should be followed:
1. Write a ‘1’ to XLD.
2. Wait 4 × N cycles. (N is the VCO frequency multiplier.)
3. Read XLD.
1 = Crystal reference is not active
0 = Crystal reference is active
The crystal loss detect function works only when the BCS bit is set,
selecting CGMVCLK to drive CGMOUT. When BCS is clear, XLD
always reads as ‘0’.
PBWC[3:0] — Reserved for test
These bits enable test functions not available in user mode. To ensure
software portability from development systems to user applications,
software should write zeros to PBWC[3:0] whenever writing to PBWC.
MC68HC08AZ0
124
Clock Generator Module (CGM)
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