MC68HC08AZ0 Datasheet, PDF (73/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
CPU registers
NOTE:
The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page zero ($0000 to $00FF) frees direct
address (page zero) space. For correct operation, the stack pointer must
point only to RAM locations.
Program counter
(PC)
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
Bit
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read:
PC
Write:
Reset:
Loaded with vector from $FFFE and $FFFF
Figure 1. Program counter (PC)
Condition code
register (CCR)
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
5 are set permanently to ‘1’. The following paragraphs describe the
functions of the condition code register.
Bit 7
6
5
4
3
2
Read:
CCR
V
1
1
H
I
N
Write:
Reset: X
1
1
X
1
X
X = Indeterminate
Figure 1. Condition code register (CCR)
1
Bit 0
Z
C
X
X
5-cpu
MOTOROLA
Central Processor Unit (CPU)
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MC68HC08AZ0
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