MC68HC08AZ0 Datasheet, PDF (294/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Timer Interface Module B (TIMB)
TRST — TIMB reset bit
Setting this write-only bit resets the TIMB counter and the TIMB
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIMB counter is reset and always reads as logic zero. Reset
clears the TRST bit.
1 = Prescaler and TIMB counter cleared
0 = No effect
NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIMB
counter at a value of $0000.
PS[2:0] — Prescaler select bits
These read/write bits select either the PTD5/ATD13 pin or one of the
seven prescaler outputs as the input to the TIMB counter as Table 1
shows. Reset clears the PS[2:0] bits.
Table 1. Prescaler selection
PS[2:0]
000
001
010
011
100
101
110
111
TIMB Clock Source
Internal Bus Clock ÷1
Internal Bus Clock ÷ 2
Internal Bus Clock ÷ 4
Internal Bus Clock ÷ 8
Internal Bus Clock ÷ 16
Internal Bus Clock ÷ 32
Internal Bus Clock ÷ 64
PTD4/ATD12/TBLCK
TIMB counter
registers
(TBCNTH:TBCNTL)
The two read-only TIMB counter registers contain the high and low bytes
of the value in the TIMB counter. Reading the high byte (TBCNTH)
latches the contents of the low byte (TBCNTL) into a buffer. Subsequent
reads of TBCNTH do not affect the latched TBCNTL value until TBCNTL
is read. Reset clears the TIMB counter registers. Setting the TIMB reset
bit (TRST) also clears the TIMB counter registers.
MC68HC08AZ0
292
Timer Interface Module B (TIMB)
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