MC68HC08AZ0 Datasheet, PDF (139/444 Pages) Motorola, Inc – Advance Information

3-maskops
MOTOROLA
Freescale Semiconductor, Inc.
Mask Options
Functional description
SEC — ROM security bit
SEC enables the ROM security feature. Setting the SEC bit prevents
access to the ROM contents.
1 = ROM security enabled
0 = ROM security disabled
The ROM security feature is disabled on the MC68HC08AZ0.
LVIRSTD — LVI reset disable bit
LVIRSTD disables the reset signal from the LVI module. See
Low-Voltage Inhibit (LVI) on page 165.
1 = LVI module resets disabled
0 = LVI module resets enabled
The reset signal from the LVI module is enabled on the MC68HC08AZ0.
LVIPWRD — LVI power disable bit
LVIPWRD disables the LVI module. See Low-Voltage Inhibit (LVI) on
page 165.
1 = LVI module power disabled
0 = LVI module power enabled
The LVI module power is enabled on the MC68HC08AZ0.
SSREC — Short stop recovery bit
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay.
1 = STOP mode recovery after 32 CGMXCLK cycles
0 = STOP mode recovery after 4096 CGMXCLK cycles
If using an external crystal oscillator, the SSREC bit should not be set.
STOP mode recovery is after 4096 CGMXCLK cycles on the
MC68HC08AZ0.
COPRS — COP rate select
COPRS is similar to COPL (please note that the logic is reversed) as
it determines the timeout period for the COP.
1 = COP timeout period is 2¹⁸ — 2⁴ CGMXCLK cycles.
0 = COP timeout period is 2¹³ — 2⁴ CGMXCLK cycles.
The COP mode timeout period is 2¹⁸ — 2⁴ CGMXCLK cycles on the
MC68HC08AZ0.
Mask Options
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MC68HC08AZ0
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