MC68HC08AZ0 Datasheet, PDF (405/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Specifications
5.0 vdc ± 0.5v Serial Peripheral Interface (SPI) Timing
5.0 vdc ± 0.5v Serial Peripheral Interface (SPI) Timing
Num
Characteristic
Symbol
Min
Max Unit
Operating Frequency (see Note 3)
Master
Slave
Cycle Time
1
Master
Slave
2 Enable Lead Time
3 Enable Lag Time
Clock (SCK) High Time
4
Master
Slave
Clock (SCK) Low Time
5
Master
Slave
Data Setup Time (Inputs)
6
Master
Slave
Data Hold Time (Inputs)
7
Master
Slave
Access Time, Slave (see Note 4)
8
CPHA = 0
CPHA = 1
9
Slave Disable Time (Hold Time to High-Impedance
State) (see Note 5)
f_BUS(M)
f_BUS(S)
f_BUS/128
dc
f_BUS/2
f_BUS
MHz
t_cyc(M)
t_cyc(S)
t_Lead
t_Lag
2
128
t_cyc
1
—
15
—
ns
15
—
ns
t_W(SCKH)M
100
t_W(SCKH)S
50
—
ns
—
t_W(SCKL)M
100
t_W(SCKL)S
50
—
ns
—
t_SU(M)
45
—
ns
t_SU(S)
5
—
t_H(M)
t_H(S)
0
—
ns
15
—
t_A(CP0)
0
40
ns
t_A(CP1)
0
20
t_DIS
—
25
ns
Data Valid Time after Enable Edge (see Note 6)
10 Master
Slave
t_V(M)
t_V(S)
—
10
ns
—
40
Data Hold Time (Outputs, after Enable Edge)
11 Master
Slave
t_HO(M)
0
—
ns
t_HO(S)
5
—
1. All timing is shown with respect to 30% V_DD and 70% V_DD, unless otherwise noted; assumes 100 pF load on all SPI
pins.
2. Item numbers refer to dimensions in Figure 1 and Figure 2.
3. f_BUS = the currently active bus frequency for the microcontroller.
4. Time to data active from high-impedance state.
5. Hold time to high-impedance state.
6. With 100 pF on all SPI pins
7-specs
MOTOROLA
Specifications
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MC68HC08AZ0
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