MC68HC08AZ0 Datasheet, PDF (91/444 Pages) Motorola, Inc – Advance Information

Bus timing
Freescale Semiconductor, Inc.
System Integration Module (SIM)
SIM bus clock control and generation
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. See Clock Generator Module (CGM) on page 107.
Clock start-up
from POR or LVI
reset
When the power-on reset module or the low-voltage inhibit module
generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after the 4096 CGMXCLK cycle POR
timeout has been completed. The RST pin is driven low by the SIM
during this entire period. The IBUS clocks start upon completion of the
timeout.
Clocks in STOP
and WAIT mode
Upon exit from STOP mode (by an interrupt, break, or reset), the SIM
allows CGMXCLK to clock the SIM counter. The CPU and peripheral
clocks do not become active until after the STOP delay timeout. This
timeout is selectable as 4096 or 32 CGMXCLK cycles. See STOP mode
on page 102.
In WAIT mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the WAIT mode subsection of
each module to see if the module is active or inactive in WAIT mode.
Some modules can be programmed to be active in WAIT mode.
5-sim
MOTOROLA
System Integration Module (SIM)
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MC68HC08AZ0
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