MC68HC08AZ0 Datasheet, PDF (169/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI)
Functional description
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
V_DD
LVIPWRD
(FROM MOR)
CPU CLOCK
LOW V_DD
DETECTOR
V_DD > LVI_TRIP = 0
V_DD < LVI_TRIP = 1
V_DD
DIGITAL FILTER
(FROM MOR)
LVIRSTD
LVI RESET
ANLGTRIP
LVIOUT
Figure 1. LVI module block diagram
Table 1. LVI I/O register summary
Register Name
Bit 7 6
5
4
3
2
LVI Status Register (LVISR) LVIOUT
= Unimplemented
1 Bit 0 Addr.
$FE0F
Polled LVI
operation
Forced reset
operation
In applications that can operate at V_DD levels below the LVI_TRIPF level,
software can monitor V_DD by polling the LVIOUT bit. In the mask option
register, the LVIPWRD and LVIRSTD bits must be at ‘0’ to enable the
LVI module and to enable the LVI resets. Also, the LVIPRWD bit must
be at ‘0’ to enable the LVI module, and the LVIRSTD bit must be at ‘1’ to
disable LVI resets.
In applications that require V_DD to remain above the LVI_TRIPF level,
enabling LVI resets allows the LVI module to reset the MCU when V_DD
falls to the LVI_TRIPF level and remains at or below that level for 9 or more
consecutive CPU cycles. In the mask option register, the LVIPWRD and
LVIRSTD bits must be at ‘0’ to enable the LVI module and to enable LVI
resets.
3-lvi
MOTOROLA
Low-Voltage Inhibit (LVI)
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MC68HC08AZ0
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