MC68HC08AZ0 Datasheet, PDF (114/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
PLL circuits
MC68HC08AZ0
112
The PLL consists of the following circuits:
• Voltage-controlled oscillator (VCO)
• Modulo VCO frequency divider
• Phase detector
• Loop filter
• Lock detector
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, f_VRS.
Modulating the voltage on the CGMXFC pin changes the frequency
within this range. By design, f_VRS is equal to the nominal center-of-range
frequency, f_NOM, (4.9152MHz) times a linear factor L, or (L)f_NOM.
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a frequency f_RCLK, and is fed to the PLL through a
buffer. The buffer output is the final reference clock, CGMRDV, running
at a frequency f_RDV = f_RCLK.
The VCO’s output clock, CGMVCLK, running at a frequency f_VCLK, is fed
back through a programmable modulo divider. The modulo divider
reduces the VCO clock by a factor N. The divider’s output is the VCO
feedback clock, CGMVDV, running at a frequency f_VDV = f_VCLK/N. (See
Programming the PLL on page 115 for more information).
The phase detector then compares the VCO feedback clock, CGMVDV,
with the final reference clock, CGMRDV. A correction pulse is generated
based on the phase difference between the two signals. The loop filter
then slightly alters the DC voltage on the external capacitor connected
to CGMXFC based on the width and direction of the correction pulse.
The filter can make fast or slow corrections depending on its mode,
described in Acquisition and tracking modes on page 113. The value of
the external capacitor and the reference frequency determines the
speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
Clock Generator Module (CGM)
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6-cgm
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