MC68HC08AZ0 Datasheet, PDF (42/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
EBI
Module I/O signal descriptions
Below is a description of the I/O signals shown in Figure 6. The External
Bus Interface module is connected to the HC08 Bus (IBUS) with data
bus IDB[7:0], address bits IAB[15:0] and IRW, IWS for control. It is
connected to the external devices with Address Bus A[15:0], Data Bus
D[7:0], and Control Bits WEB, REB, CS1 and CS0. In addition WSCLK
is provided for cycle-by-cycle external WAIT state selection.
Internal Address Ð The internal address bits are an input to the EBI module.
IAB[15:0]
Internal data Ð
IDB[7:0]
The internal data bits are bidirectional signals to the EBI module. They
are used to transfer data in and out of the EBI via the IBUS. The direction
of the data flow is controlled by the IRW signal. When IRW is high (read
mode), the data bus is an output of the EBI and the data in D[7:0] is
transferred to IDB[7:0] (the internal data bus). When IRW is low (write
mode), the data bus is an input to the EBI and the data in IDB[7:0] is
transferred to D[7:0] (the external data bus). An exception to this occurs
when the IRV bit is set. In that mode, when internal accesses occur, data
on IDB[7:0] is transferred out on D[7:0].
Internal read/write
Ð IRW
The internal read/write bit is an input control signal to the EBI module. It
allows the CPU (or DMA) to read and write to the external devices. With
the proper interface logic, the IRW generates the external read signal
REB and external write signal WEB.
External access
(External)
The External signal identifies those cycles that are not internal to the
part. This is used to keep the EBI outputs quiet for internal accesses in
Low Noise Mode.
EBIEN Ð EBI enable
The EBI enable signal is provided by physical Mask Option. It is used to
disable the EBI and therefore reduce power and RF emissions in
non-expanded mode.
MC68HC08AZ0
40
EBI
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