MC68HC08AZ0 Datasheet, PDF (403/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Specifications
Control Timing
1.V_DD = 5.0 Vdc ± 0.5v, V_SS = 0 Vdc, T_A = –40 °C to T_{A (MAX)}, unless otherwise noted.
2.Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3.Run (Operating) I_DD measured using external square wave clock source (f_OP = 8.4 MHz). All inputs 0.2 V from rail.
No dc loads. Less than 100 pF on all outputs. C_L = 20 pF on OSC2. All ports configured as inputs. OSC2 capaci-
tance linearly affects run I_DD. Measured with all modules enabled.
4.Wait I_DD measured using external square wave clock source (f_OP = 8.4 MHz). All inputs 0.2 Vdc from rail. No dc
loads. Less than 100 pF on all outputs, C_L = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance
linearly affects wait I_DD. Measured with all modules enabled.
5.Stop I_DD measured with OSC1 = V_SS.
6.Maximum is highest voltage that POR is guaranteed.
7.Maximum is highest voltage that POR is possible.
8.If minimum V_DD is not reached before the internal POR reset is released, RST must be driven low externally until
minimum V_DD is reached.
9.See Computer Operating Properly Module (COP) on page 159.
10.Although I_DD is proportional to bus frequency, a current of several mA is present even at very low frequencies.
Control Timing
Characteristic
Symbol
Min
Max
Unit
Bus Operating Frequency (4.5–5.5 V — V_DD Only)
f_BUS
—
8.4
MHz
RESET Pulse Width Low
t_RL
1.5
—
t_cyc
IRQ Interrupt Pulse Width Low (Edge-Triggered)
t_ILHI
1.5
—
t_cyc
IRQ Interrupt Pulse Period
t_ILIL
Note 3
—
t_cyc
EEPROM Programming Time per Byte
t_EEPGM
10
—
ms
EEPROM Erasing Time per Byte
t_EBYTE
10
—
ms
EEPROM Erasing Time per Block
t_EBLOCK
10
—
ms
EEPROM Erasing Time per Bulk
t_EBULK
10
—
ms
EEPROM Programming Voltage Discharge Period
t_EEFPV
100
200
µs
16-Bit Timer (see Note 2)
Input Capture Pulse Width (see Note 3)
Input Capture Period
t_TH, t_TL
2
—
t_cyc
t_TLTL
Note 4
—
MSCAN Wake-up Filter Pulse Width (see Note 5)
t_WUP
2
5
µs
1.V_DD = 5.0 Vdc ± 0.5v, V_SS = 0 Vdc, T_A = –40 °C to T_{A (MAX)}, unless otherwise noted.
2.The 2-bit timer prescaler is the limiting factor in determining timer resolution.
3.Refer to Mode, edge, and level selection on page 296 and supporting note.
4.The minimum period t_TLTL or t_ILIL should not be less than the number of cycles it takes to execute the capture interrupt
service routine plus TBD t_cyc.
5. The minimum pulse width to wake up the MSCAN module is guaranteed by design but not tested.
5-specs
MOTOROLA
Specifications
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MC68HC08AZ0
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