MC68HC08AZ0 Datasheet, PDF (315/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
I/O registers
I/O registers
The following I/O registers control and monitor operation of the ADC:
• ADC status and control register (ADSCR)
• ADC data register (ADR)
• ADC clock register (ADCLK)
ADC status and
control register
(ADSCR)
The following paragraphs describe the function of the ADC Status and
Control Register.
Bit 7
ADSCR
$0038
Read:
Write:
COCO/
IDMAS
R
Reset: 0
6
AIEN
0
5
ADCO
0
4
CH4
1
3
CH3
1
2
CH2
1
1
CH1
1
Bit 0
CH0
1
Figure 2. ADC status and control register
COCO/IDMAS — Conversions complete/interrupt DMA select
When AIEN bit is a logic zero, the COCO/IDMAS is a read only bit
which is set each time a conversion is completed except in the
continuous conversion mode where it is set after the first conversion.
This bit is cleared whenever the ADC Status and Control Register is
written or whenever the ADC Data Register is read.
If AIEN bit is a logic one, the COCO/IDMAS is a read/write bit which
selects either CPU or DMA to service the ADC interrupt request.
Reset clears this bit.
1 = conversion completed (AIEN=0) / DMA interrupt (AIEN=1)
0 = conversion not completed (AIEN=0) / CPU interrupt (AIEN=1)
7-adc
MOTOROLA
Analog-to-Digital Converter (ADC)
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MC68HC08AZ0
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