MC68HC08AZ0 Datasheet, PDF (45/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
EBI
Externally controlled WAIT states
When a chip-select is enabled, it is active for all memories and I/O cycles
within its defined (external) area. Each chip-select has control bits for
enabling, polarity setting and for inserting the correct number of WAIT
states in each bus cycle. Out of reset CS0 and CS1 are configured with
the maximum number (3) of software controlled WAIT states.
All bus timing interface signals are handled by the bus timing interface
logic that generates the proper signals for reads and writes required to
interface the internal and external buses.
Externally controlled WAIT states
The EBI generates an IWS signal which can be controlled either
internally or externally for CS0. The external option allows the user to
further decode the CS0 address space into smaller address ranges for
multiple external devices, and assign a different number of WAIT states
to each address range. The number of WAIT states associated with CS1
address space is determined internally by the CS1WS 1:0 bits.
During T4 the HC08 data bus is not driven and during this clock phase
the number of WAIT states for the cycle in progress is determined. When
CS0 is asserted, the value on the External Data bus at the end of T4 is
used to determine the number of WAIT States according to Table 2 This
WAIT state value is encoded in the first 3 bits of the data bus, D2:0. This
mode of operation is selected by enabling the function in the EBI control
register and by enabling the WSCLK pin according to Table 3 The WAIT
state value on the data bus is only latched when CS0 is asserted.
Therefore, it is not required that the bus be driven during T4 when
accessing addresses outside the CS0 range (i.e. when CS1 is asserted).
The WAIT state value driven onto the External Data bus may be derived
directly from the address lines or indirectly from a decoded chip select
signal(s). In all cases, the WAIT state value must only be allowed to drive
the External Data bus during the period WSCLK is asserted by using a
tri-statable buffer (e.g. 74AC240/244, 74AC367A/368A, 74AC125). See
examples later in this section.
7-ebi
MOTOROLA
EBI
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MC68HC08AZ0
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