MC68HC08AZ0 Datasheet, PDF (209/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Communications Interface Module (SCI)
I/O registers
DMATE — DMA transfer enable bit
This read/write bit enables SCI transmitter empty (SCTE) DMA
service requests. <blue>See SCI status register 1 (SCS1). Setting
the DMATE bit disables SCTE CPU interrupt requests. Reset clears
DMATE.
1 = SCTE DMA service requests enabled (SCTE CPU interrupt
requests disabled)
0 = SCTE DMA service requests disabled (SCTE CPU interrupt
requests enabled)
ORIE — Receiver overrun interrupt enable bit
This read/write bit enables SCI error CPU interrupt requests
generated by the receiver overrun bit, OR.
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
NEIE — Receiver noise error interrupt enable bit
This read/write bit enables SCI error CPU interrupt requests
generated by the noise error bit, NE. Reset clears NEIE.
1 = SCI error CPU interrupt requests from NE bit enabled.
0 = SCI error CPU interrupt requests from NE bit disabled
FEIE — Receiver framing error interrupt enable bit
This read/write bit enables SCI error CPU interrupt requests
generated by the framing error bit, FE. Reset clears FEIE.
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
PEIE — Receiver parity error interrupt enable bit
This read/write bit enables SCI receiver CPU interrupt requests
generated by the parity error bit, PE. (see SCI status register 1
(SCS1) on page 208). Reset clears PEIE.
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
29-sci
MOTOROLA
Serial Communications Interface Module (SCI)
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MC68HC08AZ0
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