MC68HC08AZ0 Datasheet, PDF (51/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
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Externally controlled WAIT states
In Figure 10, the application has several external peripheral devices
which are decoded into the CS0 address space using an external 3-to-8
decoder (e.g. 74AC138). The addition of a tri-stateable buffer (e.g.
74AC367, hex buffer) represents the hardware overhead to provide a
unique number of WAIT states for each decoded address space.
Decoder outputs provide the peripheral chip selects. In this
implementation, the same addresses used by the decoder are driven
back onto the data bus during T4. Therefore, as the address increments,
so does the number of WAIT states assigned to each address space.
WSCLK is configured to drive CS0+T4, which drives the buffer enables
during T4 when the address is within the CS0 range.
Choosing to drive different addresses onto the data bus during T4 allow
the user to provide a different mix of WAIT states throughout the
decoded CS0 address space. Alternatively, the 3-8 line decoder could
be replaced with a PAL which would provide for a more complex decode
and assignment of WAIT states. The number of WAIT states for CS1 is
selected internally based on the contents of CS1WS1:0 bits and may
between 0 and 3 bus cycles.
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MC68HC08AZ0
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