MC68HC08AZ0 Datasheet, PDF (130/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Special modes
The WAIT and STOP instructions put the MCU in
low-power-consumption standby modes.
WAIT mode
The WAIT instruction does not affect the CGM. Before entering WAIT
mode, software can disengage and turn off the PLL by clearing the BCS
and PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications
that require the PLL to wake the MCU from WAIT mode also can
deselect the PLL output without turning off the PLL.
STOP mode
When the STOP instruction executes, the SIM drives the SIMOSCEN
signal low, disabling the CGM and holding low all CGM outputs
(CGMXCLK, CGMOUT, and CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK,
divided by two driving CGMOUT, the PLL automatically clears the BCS
bit in the PLL control register (PCTL), thereby selecting the crystal clock,
CGMXCLK, divided by two as the source of CGMOUT. When the MCU
recovers from STOP, the crystal clock divided by two drives CGMOUT
and BCS remains clear.
MC68HC08AZ0
128
Clock Generator Module (CGM)
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22-cgm
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