MC68HC08AZ0 Datasheet, PDF (226/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
A slave SPI must complete the write to the data register at least one bus
cycle before the master SPI starts a transmission. When the clock phase
bit (CPHA) is set, the first edge of SPSCK starts a transmission. When
CPHA is clear, the falling edge of SS starts a transmission. See
Transmission formats on page 225.
If the write to the data register is late, the SPI transmits the data already
in the shift register from the previous transmission.
NOTE: SPSCK must be in the proper idle state before the slave is enabled to
prevent SPSCK from appearing as a clock edge.
MC68HC08AZ0
224
Serial Peripheral Interface Module (SPI)
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