MC68HC08AZ0 Datasheet, PDF (392/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
msCAN08 Controller (msCAN08)
RXFIE — Receiver Full Interrupt Enable
1 = A receive buffer full (successful message reception) event will
result in a receive interrupt.
0 = No interrupt will be generated from this event.
NOTE: The CRIER register is held in the reset state when the SFTRES bit in
CMCR0 is set.
msCAN08
Transmitter Flag
Register (CTFLG)
All bits of this register are read and clear only. A flag can be cleared by
writing a 1 to the corresponding bit position. Writing a 0 has no effect on
the flag setting. Every flag has an associated interrupt enable flag in the
CTCR register. A hard or soft reset will clear the register.
CTFLG R
$xx06 W
RESET
BIT 7
0
0
BIT 6
BIT 5
BIT 4
ABTAK2 ABTAK1 ABTAK0
BIT 3
0
BIT 2
TXE2
0
0
0
0
1
= Unimplemented
Figure 21. Transmitter Flag Register
BIT 1
TXE1
1
BIT 0
TXE0
1
MC68HC08AZ0
390
ABTAK2–ABTAK0 — Abort Acknowledge
This flag acknowledges that a message has been aborted due to a
pending abort request from the CPU. After a particular message
buffer has been flagged empty, this flag can be used by the
application software to identify whether the message has been
aborted successfully or has been sent in the meantime. The flag is
reset implicitly whenever the associated TXE flag is set to 0.
1 = The message has been aborted.
0 = The massage has not been aborted, thus has been sent out.
TXE2–TXE0 —Transmitter Buffer Empty
This flag indicates that the associated transmit message buffer is
empty, thus not scheduled for transmission. The CPU must
handshake (clear) the flag after a message has been set up in the
transmit buffer and is due for transmission. The msCAN08 will set the
flag after the message has been sent successfully. The flag will also
be set by the msCAN08 when the transmission request was
msCAN08 Controller (msCAN08)
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