MC68HC08AZ0 Datasheet, PDF (106/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
System Integration Module (SIM)
SIM registers
The SIM has three memory mapped registers. Table 4 shows the
mapping of these registers.
Address
$FE00
$FE01
$FE03
Table 4. SIM Registers
Register
SBSR
SRSR
SBFCR
Access mode
User
User
User
SIM break status
register (SBSR)
The SIM break status register contains a flag to indicate that a break
caused an exit from STOP or WAIT mode.
SBSR
$FE00
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
SBSW
R
R
R
R
R
R
R
Note⁽¹⁾
0
R = Reserved for factory test
1. Writing a logic ‘0’ clears SBSW.
Figure 16. SIM break status register (SBSR)
SBSW — SIM Break STOP/WAIT
This status bit is useful in applications requiring a return to STOP or
WAIT mode after exiting from a break interrupt. SBSW can be cleared
by writing a logic ‘0’ to it. Reset clears SBSW.
1 = STOP or WAIT mode was exited by break interrupt
0 = STOP or WAIT mode was not exited by break interrupt
MC68HC08AZ0
104
System Integration Module (SIM)
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20-sim
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