MC68HC08AZ0 Datasheet, PDF (248/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
SPI status and
control register
(SPSCR)
The SPI status and control register contains flags to signal the following
conditions:
• Receive data register full
• Failure to clear SPRF bit before next byte is received (overflow
error)
• Inconsistent logic level on SS pin (mode fault error)
• Transmit data register empty
The SPI status and control register also contains bits that perform the
following functions:
• Enable error interrupts
• Enable mode fault error detection
• Select master SPI baud rate
Bit 7
6
5
4
3
2
1
SPSCR
Read: SPRF
Write: R
ERRIE
OVRF
R
MODF
R
SPTE
R
MODFE
N
SPR1
Reset: 0
0
0
0
1
0
0
R = Reserved
Figure 14. SPI status and control register (SPSCR)
Bit 0
SPR0
0
SPRF — SPI receiver full
This clearable, read-only flag is set each time a byte transfers from
the shift register to the receive data register. SPRF generates a CPU
interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the
SPI status and control register with SPRF set and then reading the
SPI data register. During an SPRF DMA transmission (DMAS=’1’),
any read of the SPI data register clears the SPRF bit.
Reset clears the SPRF bit.
1 = Receive data register full
0 = Receive data register not full
MC68HC08AZ0
246
Serial Peripheral Interface Module (SPI)
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