MC68HC08AZ0 Datasheet, PDF (205/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Communications Interface Module (SCI)
I/O registers
SCC2
$0014
Bit 7
6
5
4
3
2
Read:
SCTIE TCIE SCRIE ILIE
TE
RE
Write:
Reset: 0
0
0
0
0
0
Figure 6. SCI control register 2 (SCC2)
1
Bit 0
RWU SBK
0
0
SCTIE — SCI transmit interrupt enable bit
This read/write bit enables the SCTE bit to generate SCI transmitter
CPU interrupt requests or DMA service requests. Setting the SCTIE
bit and clearing the DMA transfer enable bit, DMATE, in SCC3
enables the SCTE bit to generate CPU interrupt requests. Setting
both the SCTIE and DMATE bits enables the SCTE bit to generate
DMA service requests. Setting both SCRIE and DMARE enables
SCRF to generate DMA service requests. Reset clears the SCTIE bit.
1 = SCTE enabled to generate CPU interrupt or DMA service
requests
0 = SCTE not enabled to generate CPU interrupt or DMA service
requests
TCIE — Transmission complete interrupt enable bit
This read/write bit enables the TC bit to generate SCI transmitter CPU
interrupt requests. Reset clears the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
SCRIE — SCI receive interrupt enable bit
This read/write bit enables the SCRF bit to generate SCI receiver
CPU interrupt requests or SCI receiver DMA service requests. Setting
the SCRIE bit and clearing the DMA receive enable bit, DMARE,in
SCC3 enables the SCRF bit to generate CPU interrupt requests.
Reset clears the SCRIE bit.
1 = SCRF enabled to generate CPU interrupt or DMA service
requests
0 = SCRF not enabled to generate CPU interrupt or DMA service
requests
25-sci
MOTOROLA
Serial Communications Interface Module (SCI)
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MC68HC08AZ0
203