MC68HC08AZ0 Datasheet, PDF (302/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Programmable Interrupt Timer (PIT)
Functional Description
Figure 1 shows the structure of the PIT. The central component of the
PIT is the 16-bit PIT counter that can operate as a free-running counter
or a modulo up-counter. The counter provides the timing reference for
the interrupt. The PIT counter modulo registers, PMODH:PMODL, con-
trol the modulo value of the counter. Software can read the counter
value at any time without affecting the counting sequence.
INTERNAL
BUS CLOCK
PRESCALER
CSTOP
CRST
16-BIT COUNTER
16-BIT COMPARATOR
PITTMODH:PITTMODL
PRESCALER SELECT
PPS2 PPS1 PPS0
POF
PIE
Figure 1. PIT Block Diagram
INTERRUPT
LOGIC
Table 1. PIT I/O Register Summary
Register Name
Bit 7 6
5
4
3
2
1 Bit 0 Addr.
PIT Status/Control Register (PSC) POF PIE PSTOP PRST 0 PPS2 PPS1 PPS0 $004B
PIT Counter Register. High (PCNTH) Bit 15 14 13 12 11 10
9
8 $004C
PIT Counter Register. Low (PCNTL) 7
6
5
4
3
2
1
0 $004D
PIT Counter Modulo Reg. High (PMODH) Bit 15 14 13 12 11 10
9 Bit 8 $004E
PIT Counter Modulo Reg. Low (PMODL) Bit 7 6
5
4
3
2
1 Bit 0 $004F
MC68HC08AZ0
300
Programmable Interrupt Timer (PIT)
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2-pit
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