MC68HC08AZ0 Datasheet, PDF (168/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI)
Features
Features of the LVI module include the following:
• Programmable LVI reset
• Programmable power consumption
• Digital filtering of VDD pin level
NOTE:
If a low voltage interrupt (LVI) occurs during programming of EEPROM
memory, then adequate programming time may not have been allowed
to ensure the integrity and retention of the data. It is the responsibility of
the user to ensure that in the event of an LVI any addresses being
programmed receive specification programming conditions.
Functional description
Figure 1 shows the structure of the LVI module. The LVI is enabled out
of reset. The LVI module contains a bandgap reference circuit and
comparator. The LVI power bit, LVIPWRD, enables the LVI to monitor
V_DD voltage. The LVI reset bit, LVIRSTD, enables the LVI module to
generate a reset when V_DD falls below a voltage, LVI_TRIPF, and remains
at or below that level for 9 or more consecutive CPU cycles.
Note that short V_DD spikes may not trip the LVI. It is the user’s
responsibility to ensure a clean V_DD signal within the specified
operating voltage range if normal microcontroller operation is to be
guaranteed.
LVIPWRD and LVIRSTD are mask options. See Mask Options on page
135. Once an LVI reset occurs, the MCU remains in reset until V_DD rises
above a voltage, LVI_TRIPR. V_DD must be above LVI_TRIPR for only one CPU
cycle to bring the MCU out of reset. The output of the comparator
controls the state of the LVIOUT flag in the LVI status register (LVISR).
MC68HC08AZ0
166
Low-Voltage Inhibit (LVI)
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