MC68HC08AZ0 Datasheet, PDF (144/444 Pages) Motorola, Inc – Advance Information

Break Module
Freescale Semiconductor, Inc.
CPU during break
interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD
in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
DMA during break
interrupts
During a break interrupt, the DMA is inactive.
If a DMA-generated address matches the contents of the break address
registers, a break interrupt begins at the end of the current CPU
instruction.
If a break interrupt is asserted during the current address cycle and the
DMA is active, the DMA releases the internal address and data buses at
the next address boundary to preserve the current MCU state. During
the break interrupt, the DMA continues to arbitrate DMA channel
priorities. After the break interrupt, the DMA becomes active again and
resumes transferring data according to its highest priority service
request.
TIM and PIT during A break interrupt stops the timer counter.
break interrupts
COP during break The COP is disabled during a break interrupt when V_HI is present on the
interrupts
RST pin.
MC68HC08AZ0
142
Break Module
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