MC68HC08AZ0 Datasheet, PDF (393/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
msCAN08 Controller (msCAN08)
Programmer’s model of control registers
successfully aborted due to a pending abort request (see msCAN08
Transmitter Control Register (CTCR) on page 391). If not masked, a
Transmit interrupt is pending while this flag is set.
A reset of this flag will also reset the Abort Acknowledge (ABTAK,
see above) and the Abort Request (ABTRQ) (see msCAN08 Trans-
mitter Control Register (CTCR) on page 391), flags of the particular
buffer.
1 = The associated message buffer is empty (not scheduled).
0 = The associated message buffer is full (loaded with a message
due for transmission).
NOTE: The CTFLG register is held in the reset state when the SFTRES bit in
CMCR0 is set.
msCAN08
Transmitter Control
Register (CTCR)
CTCR R
$xx07 W
RESET
BIT 7
0
0
BIT 6
BIT 5
BIT 4
ABTRQ2 ABTRQ1 ABTRQ0
BIT 3
0
BIT 2
TXEIE2
0
0
0
0
0
= Unimplemented
Table 9. Transmitter Control Register
BIT 1
TXEIE1
0
BIT 0
TXEIE0
0
ABTRQ2–ABTRQ0 — Abort Request
The CPU sets this bit to request that an already scheduled message
buffer (TXE = 0) shall be aborted. The msCAN08 will grant the
request when the message is not already under transmission. When
a message is aborted the associated TXE and the Abort
Acknowledge flag ABTAK) (see msCAN08 Transmitter Flag Register
(CTFLG) on page 390), will be set and an TXE interrupt will occur if
enabled. The CPU can not reset ABTRQx. ABTRQx is reset implicitly
whenever the associated TXE flag is set.
1 = Abort request pending.
0 = No abort request.
41-can
MOTOROLA
msCAN08 Controller (msCAN08)
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MC68HC08AZ0
391