MC68HC08AZ0 Datasheet, PDF (344/444 Pages) Motorola, Inc – Advance Information

I/O Ports
Freescale Semiconductor, Inc.
TxD — SCI transmit data output
The PTE0/TxD pin is the transmit data output for the SCI module.
When the enable SCI bit, ENSCI, is clear, the SCI module is disabled,
and the PTE0/TxD pin is available for general-purpose I/O. See SCI
Control Register 2 (SCC2) on page 202.
NOTE:
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SCI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. See Table 6.
Data direction
register E (DDRE)
Data direction register E determines whether each port E pin is an input
or an output. Writing a logic one to a DDRE bit enables the output buffer
for the corresponding port E pin; a logic zero disables the output buffer.
Bit 7
6
5
4
3
2
1
Bit 0
DDRE
$000C
Read:
DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 14. Data direction register E (DDRE)
DDRE[7:0] — Data direction register E bits
These read/write bits control port E data direction. Reset clears
DDRE[7:0], configuring all port E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE: Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 15 shows the port E I/O logic.
When bit DDREx is a logic one, reading address $0008 reads the PTEx
data latch. When bit DDREx is a logic zero, reading address $0008
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 6 summarizes the
operation of the port E pins.
MC68HC08AZ0
342
I/O Ports
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