MC68HC08AZ0 Datasheet, PDF (237/444 Pages) Motorola, Inc – Advance Information

ERRIE
MODF
OVRF
Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
Queuing transmission data
SPTE SPTIE SPE
SPI TRANSMITTER
CPU INTERRUPT REQUEST
SPRIE SPRF
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
Figure 10. SPI interrupt request generation
Two sources in the SPI status and control register can generate CPU
interrupt requests:
• SPI receiver full bit (SPRF) — the SPRF bit becomes set every
time a byte transfers from the shift register to the receive data
register. If the SPI receiver interrupt enable bit, SPRIE, is also set,
SPRF can generate either an SPI receiver/error CPU interrupt
request.
• SPI transmitter empty (SPTE) — the SPTE bit becomes set every
time a byte transfers from the transmit data register to the shift
register. If the SPI transmit interrupt enable bit, SPTIE, is also set,
SPTE can generate an SPTE CPU interrupt request.
Queuing transmission data
The double-buffered transmit data register allows a data byte to be
queued and transmitted. For an SPI configured as a master, a queued
data byte is transmitted immediately after the previous transmission has
completed. The SPI transmitter empty flag (SPTE) indicates when the
transmit data buffer is ready to accept new data. Write to the SPI data
register only when the SPTE bit is high. Figure 11 shows the timing
19-spi
MOTOROLA
Serial Peripheral Interface Module (SPI)
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MC68HC08AZ0
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