MC68HC08AZ0 Datasheet, PDF (299/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Timer Interface Module B (TIMB)
I/O Registers
NOTE: Before enabling a TIMB channel register for input capture operation,
make sure that the PTFx/TBCHx pin is stable for at least two bus clocks.
TOVx — Toggle-on-overflow bit
When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIMB counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIMB counter overflow.
0 = Channel x pin does not toggle on TIMB counter overflow.
NOTE: When TOVx is set, a TIMB counter overflow Takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x maximum duty cycle bit
When the TOVx bit is at logic zero, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 15 shows, the CHxMAX bit Takes effect in the cycle after it is
set or cleared. The output stabs at the 100% duty cycle level until the
cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
PERIOD
PTFx/TBCHx
OVERFLOW
OVERFLOW
OVERFLOW
CHxMAX
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 15. CHxMAX latency
21-timb
MOTOROLA
Timer Interface Module B (TIMB)
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MC68HC08AZ0
297