MC68HC08AZ0 Datasheet, PDF (108/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
System Integration Module (SIM)
PIN — External reset bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer operating properly reset bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal opcode reset bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal address reset bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
LVI — Low-voltage inhibit reset bit
1 = Last reset was caused by the LVI circuit
0 = POR or read of SRSR
SIM break flag
control register
(SBFCR)
The SIM break control register contains a bit that enables software to
clear status bits while the MCU is in a break state.
Bit 7
6
5
4
3
2
1
Bit 0
SBFCR
$FE03
Read:
Write:
BCFE
R
R
R
R
R
R
R
Reset: 0
R = Reserved for factory test
Figure 18. SIM break flag control register (SBFCR)
BCFE — break clear flag enable bit
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
MC68HC08AZ0
106
System Integration Module (SIM)
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22-sim
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