MC68HC08AZ0 Datasheet, PDF (189/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Communications Interface Module (SCI)
Functional description
Idle characters
An idle character contains all ‘1’s and has no start, stop, or parity bit.
Idle character length depends on the M bit in SCC1. The preamble is
a synchronizing idle character that begins every transmission.
If the TE bit is cleared during a transmission, the PTE2/TxD pin
becomes idle after completion of the transmission in progress.
Clearing and then setting the TE bit during a transmission queues an
idle character to be sent after the character currently being
transmitted.
NOTE:
When queueing an idle character, return the TE bit to ‘1’ before the stop
bit of the current character shifts out to the PTE0/TxD pin. Setting TE
after the stop bit appears on PTE0/TxD causes data previously written
to the SCDR to be lost.
A good time to toggle the TE bit is when the SCTE bit becomes set and
just before writing the next byte to the SCDR.
Inversion of transmitted output
The transmit inversion bit (TXINV) in SCI control register 1 (SCC1)
reverses the polarity of transmitted data. All transmitted values,
including idle, break, start, and stop bits, are inverted when TXINV is
at ‘1’. See SCI control register 1 (SCC1) on page 199.
Transmitter interrupts
The following conditions can generate CPU interrupt requests from
the SCI transmitter:
• SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates
that the SCDR has transferred a character to the transmit shift
register. SCTE can generate a transmitter CPU interrupt request
or a transmitter DMA service request. Setting the SCI transmit
interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to
generate transmitter CPU interrupt requests. Setting both the
SCTIE bit and the DMA transfer enable bit, DMATE, in SCC3
enables the SCTE bit to generate transmitter DMA service
requests.
9-sci
MOTOROLA
Serial Communications Interface Module (SCI)
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MC68HC08AZ0
187