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| MC68HC08AZ0 Datasheet, PDF (170/444 Pages) Motorola, Inc – Advance Information | |||
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Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI)
False reset
protection
The VDD pin level is digitally filtered to reduce false resets due to power
supply noise. In order for the LVI module to reset the MCU,VDD must
remain at or below the LVITRIPF level for 9 or more consecutive CPU
cycles. VDD must be above LVITRIPR for only one CPU cycle to bring the
MCU out of reset.
LVI Status Register (LVISR)
The LVI status register flags VDD voltages below the LVITRIPF level.
Bit 7
6
5
4
3
2
LVISR Read: LVIOUT
0
0
0
0
0
$FE0F Write:
Reset: 0
0
0
0
0
0
= Unimplemented
Figure 2. LVI Status Register (LVISR)
1
Bit 0
0
0
0
0
LVIOUT â LVI Output Bit
This read-only flag becomes set when VDD falls below the LVITRIPF
voltage for 32-40 CGMXCLK cycles. (See Table 2). Reset clears the
LVIOUT bit.
Table 2. LVIOUT bit indication
at level:
VDD > LVITRIPR
VDD < LVITRIPF
VDD < LVITRIPF
VDD < LVITRIPF
LVITRIPF < VDD < LVITRIPR
VDD
for number of CGMXCLK
cycles:
ANY
< 32 CGMXCLK cycles
between 32 & 40 CGMXCLK
cycles
> 40 CGMXCLK cycles
ANY
LVIOUT
0
0
0 or 1
1
Previous Value
MC68HC08AZ0
168
Low-Voltage Inhibit (LVI)
For More Information On This Product,
Go to: www.freescale.com
4-lvi
MOTOROLA
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