MC68HC08AZ0 Datasheet, PDF (104/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
System Integration Module (SIM)
IAB
$6E0B
$6E0C $00FF $00FE $00FD $00FC
IDB $A6 $A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 12. WAIT recovery from interrupt or break
IAB
$6E0B
32
Cycles
32
Cycles
RSTVCTH RSTVCTL
IDB $A6 $A6
$A6
RST
CGMXCLK
Figure 13. WAIT recovery from internal reset
STOP mode
In STOP mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from
STOP mode. Stacking for interrupts begins after the selected STOP
recovery time has elapsed. Reset or break also causes an exit from
STOP mode.
The SIM disables the clock generator module outputs (CGMOUT and
CGMXCLK) in STOP mode, stopping the CPU and peripherals. STOP
recovery time is selectable using the SSREC bit in the mask option
register (MOR). If SSREC is set, STOP recovery is reduced from the
normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for
applications using canned oscillators that do not require long start-up
times from STOP mode.
MC68HC08AZ0
102
System Integration Module (SIM)
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18-sim
MOTOROLA