MC68HC08AZ0 Datasheet, PDF (171/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI)
LVI interrupts
LVI interrupts
The LVI module does not generate interrupt requests.
Low-power modes
The WAIT instruction puts the MCU in low-power-consumption standby
mode.
WAIT mode
When the LVIPWRD mask option is programmed to ‘0’, the LVI module
is active after a WAIT instruction.
When the LVIRSTD mask option is programmed to ‘0’, the LVI module
can generate a reset and bring the MCU out of WAIT mode.
Stop Mode
With LVISTOP=1 and LVIPWRD=0 in the MORA register, the LVI
module will be active after a STOP instruction. Because CPU clocks are
disabled during stop mode, the LVI trip must bypass the digital filter to
generate a reset and bring the MCU out of stop.
With the LVIPWRD bit in the MORA register at a logic 0 and the
LVISTOP bit at a logic 0, the LVI module will be inactive after a STOP
instruction.
Note that the LVI feature is intended to provide the safe shutdown
of the microcontroller and thus protection of related circuitry prior
to any application V_DD voltage collapsing completely to an unsafe
level. Is is not intended that users operate the microcontroller at
lower than the specified operating voltage, V_DD.
5-lvi
MOTOROLA
Low-Voltage Inhibit (LVI)
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MC68HC08AZ0
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