MC68HC08AZ0 Datasheet, PDF (105/444 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
System Integration Module (SIM)
Low-power modes
NOTE: External crystal applications should use the full STOP recovery time by
clearing the SSREC bit.
A break interrupt during STOP mode sets the SIM break STOP/WAIT bit
(SBSW) in the SIM break status register (SBSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of STOP recovery. It is then used to time
the recovery period. Figure 14 shows STOP mode entry timing.
CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 14. STOP mode entry timing
CGMXCLK
INT/BREAK
IAB
STOP RECOVERY PERIOD
STOP +1
STOP + 2 STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 15. STOP mode recovery from interrupt or break
19-sim
MOTOROLA
System Integration Module (SIM)
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MC68HC08AZ0
103